FDTC 2010
August 21, 2010, Santa Barbara, CA, USA
http://conferenze.dei.polimi.it/FDTC10/


The  7th Workshop  on Fault  Diagnosis and  Tolerance  in Cryptography
(FDTC 2010) will be held in Santa Barbara, CA, USA on August 21, 2010.

FDTC 2010  is co-located with  CHES 2010 (August 17-20,  2010); itself
co-located with CRYPTO  2010 (August 15-19, 2010). Note  also the NIST
Second SHA-3 Candidate Conference (August 23-24, 2010).


MOTIVATION & SCOPE

In recent  years applied  cryptography has developed  considerably, to
satisfy  the increasing security  requirements of  various information
technology  disciplines,  e.g.,  telecommunications, networking,  data
base  systems and  mobile applications.  Cryptosystems  are inherently
computationally complex  and in order  to satisfy the  high throughput
requirements of many applications, they are often implemented by means
of  either  VLSI  devices  (crypto-accelerators) or  highly  optimised
software  routines  (crypto-libraries)   and  are  used  via  suitable
(network) protocols.

The high complexity of  such implementations raises concerns regarding
their   reliability.   Research  is   therefore   needed  to   develop
methodologies  and  techniques   for  designing  robust  cryptographic
systems (both hardware and software), and to protect them against both
accidental   faults  and  intentional   intrusions  and   attacks,  in
particular those based  on the malicious injection of  faults into the
device for the purpose of extracting the secret key.

This annual workshop  was started in 2004 and  had follow-ups in 2005,
2006, 2007, 2008 and 2009.  Paper submission

Contributions  to  the  workshop  describing theoretical  studies  and
practical   case  studies   of  fault   diagnosis  and   tolerance  in
cryptographic systems (HW and  SW) and protocols are solicited. Topics
of interest include, but are not limited to:

    * modeling the reliability of cryptographic systems and protocols;
    * inherently reliable cryptographic systems and algorithms;
    * faults and fault models for cryptographic devices (HW and SW);
    * reliability-based attack procedures on cryptographic systems
      (fault-injection attacks) and protocols; 
    * adapting classical fault diagnosis and tolerance techniques to
      cryptographic systems; 
    * novel fault diagnosis and tolerance techniques for cryptographic
      systems; 
    * attacks exploiting micro-architecture components (cache, branch
      predictor, etc.); 
    * physical protection against attacks;
    * fault injection based attacks using FIB laser and chemistry;
    * case studies of attacks, reliability and fault diagnosis and
      tolerance techniques in cryptographic systems. 

All  submissions should  be made  using the  online  submission system
(https://fdtc.ws.dei.polimi.it/ichair/). Submissions should conform to
the instructions below.


IMPORTANT DATES

Paper submission deadline: 	March 28, 2010, 23:59 UTC
Notification of acceptance: 	May 6, 2010
Final version deadline: 	June 4, 2010
Workshop: 			August 21, 2010


INSTRUCTIONS FOR AUTHORS

Submissions  must not  substantially duplicate  work that  any  of the
authors  have  published elsewhere  or  that  have  been submitted  in
parallel with any other  conference or workshop. Submissions should be
anonymous,  with  no author  names,  affiliations, acknowledgments  or
obvious references. Papers  should be at most 10  pages (including the
bibliography and  appendices), with at least 11pt  font and reasonable
margins.

Submission of final  papers will be managed directly  by IEEE Computer
Society's Conference  Publishing Services (CPS). Final  papers must be
formatted   following   the  instructions   in   the  related   author
kit. Conference  Publishing Services  (CPS) will contact  directly the
authors  for  instructions  and  will  send links  to  the  publishing
services.

At  least one author  of each  accepted paper  must register  with the
workshop  and  present  the paper  in  order  to  be included  in  the
proceedings.  


PROGRAM COMMITTEE

    * Guido Bertoni, ST Microelectronics, Italy
    * Wieland Fischer, Infineon Technologies, Germany
    * Christophe Giraud, Oberthur Technologies, France
    * Sylvain Guilley, Télécom ParisTech, France
    * Helena Handschuh, Intrinsic-ID Inc., USA
    * M. Anwar Hasan, University of Waterloo, Canada
    * Niraj K. Jha, Princeton University, USA
    * Marc Joye (co-chair), Technicolor, France
    * Ramesh Karri, Polytechnic University, USA
    * Çetin K. Koç, UC Santa Barbara, USA
    * Kerstin Lemke-Rust, Hochschule Bonn-Rhein-Sieg, Germany
    * Régis Leveugle, TIMA, France
    * Jim Plusquellic, University of New Mexico, USA
    * Akashi Satoh, AIST, Japan
    * Jörn-Marc Schmidt, Technische Universität Graz, Austria
    * Sergei Skoroboratov, University of Cambridge, UK
    * Tsuyoshi Takagi, Future University Hakodate, Japan
    * Michael Tunstall, University of Bristol, UK
    * Ingrid Verbauwhede (co-chair), K.U. Leuven, Belgium 


STEERING COMMITTEE

    * Luca Breveglieri, Politecnico di Milano, Italy
    * Israel Koren, University of Massachusetts, USA
    * David Naccache (chair), Ecole Normale Supérieure, France
    * Jean-Pierre Seifert, TU Berlin and T-Labs, Germany